1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device having a variable resistive element, which stores data due to a change in the electrical resistance through the application of voltage, on a semiconductor substrate.
2. Description of the Related Art
A technique of changing the resistance value of a material having a perovskite structure, at room temperature in a reversible manner by applying a voltage pulse to the material, which is known as a colossal magnetoresistance (CMR), is disclosed in U.S. Pat. No. 6,204,139, wherein the resistance value can be changed by a magnitude of ten times or more in a reversible manner through the application of a voltage pulse. FIG. 1 shows an example of the programming characteristics of this variable resistive element. As shown in FIG. 1, the resistance value of the variable resistive element changes depending on the magnitude of the program voltage. The resistance value can be changed by applying a voltage no less than a predetermined threshold voltage (Vth). Here, the term “threshold value” indicates the lower limit of the voltage that allows for a change in the resistance. A patent has been applied for by the applicant of the present case (JP-A 2002-185234) concerning a nonvolatile semiconductor memory device utilizing this property, and part of this content is disclosed in “Novel Colossal Magnetoresistive Thin Film Nonvolatile Resistance Random Access Memory (RRAM)”, by Zhuang, H. H. et al., IEDM, article number 7.5, December, 2002.
According to this conventional technique, a memory cell is formed of a cell selecting element and a variable resistive element. FIG. 2 shows a memory cell according to the conventional technique wherein a transistor is used as the cell selecting element.
Programming and erasing operations in a memory cell shown in FIG. 2 will be briefly described below. In the case where programming is carried out in a variable resistive element R12, program voltage is applied to a bit line B2, a bit line B1 and a source line S1 are connected to the ground and a predetermined voltage is applied to a word line W1 for approximately 100 ns and thereby, a transistor T12, which is a cell selecting element, is turned on while a program voltage is applied to the variable resistive element R12, so as to convert the variable resistive element R12 to the program condition. At the time of erasing, an erase voltage is applied to the source line S1 and the bit line B1, the bit line B2 is connected to the ground and a predetermined voltage is applied to the word line W1 for approximately 100 ns and thereby, the transistor T12 is turned on while an erase voltage is applied to the variable resistive element R12, so as to convert the variable resistive element R12 to the erase condition. At this time, the polarities of the voltage applied to the variable resistive element R12 are opposite to those at the time of programming.
As shown in FIG. 2, however, in the case where a memory cell is formed of a cell selecting element made up of a transistor and a variable resistive element, only a slight problem occurs regarding ‘disturbance’ (error programming, error erasing and the like) of the unselected memory cells, which are not to be programmed or erased, since a cell selecting element made up of a transistor is provided. However, a memory cell is provided with a cell selecting element, increasing the area of the memory cell, which causes an increase in the chip size as a result of the integration of memory cells, and which is a factor hindering an increase in the capacity of the memory.